1. Technical Field
Embodiments of the invention are generally related to memory systems, and more particularly, but not exclusively, to the configuring of reference voltages for a memory device.
2. Background Art
Integrated circuit technologies continue to evolve. Computing and communications designs are incorporating more functionality, higher processing and transmission speeds, smaller feature sizes, more memory, etc., into smaller and more robust architectures. Semiconductor memories in particular are evolving at a rapid pace. Memory devices have reduced power requirements, increased capacities, increased operating frequencies, reduced latencies, etc., all while ramping with the exponential density increases according to Moore's Law.
To reduce power or otherwise scale performance, double-data-rate (LPDDR 4), cross point memory, phase change memory (PCM) and other memory technologies are incorporating various features such as alternative termination schemes. Such schemes, which can include VDDQ or VSSQ termination, typically provide for relatively simple memory management for power efficiency under various usage models. However, these termination schemes tend to come at the expense of other performance considerations such as receive-side management of I/O signal errors. One cause of this is the susceptibility of such termination to the effects of variation in integrated circuit fabrication processing which, in turn, can reduce signaling performance. This is one reason for the growing need to provide improved techniques and mechanisms for memory systems to account for signal variation.